EKTF6708 datasheet(119/158 Pages) EMC

119 / 158 page

eKTF6708

8-Bit Microcontroller

IC Product Specification (V1.2) 03.12.2020

 109

(This specification is subject to change without prior notice)



Program the same clock rate and clock edge to latch on both Master and Slave devices.



The byte received will update the transmitted byte.



The RBF will be set as the SPI operation is completed.



Timing is shown in Figures 6-10a and 6-10b below.

 P52/SO:



Serial Data Out



Transmit sequentially; the Most Significant Bit (MSB) first, Least Significant Bit (LSB)

last.



Program the same clock rate and clock edge to latch on both the Master and Slave

devices.



The received byte will update the transmitted byte.



The CES bit is reset, as the SPI operation is completed.



Timing is shown in Figures 6-10a and 6-10b.

 P53/SCK:



Serial Clock



Generated by a Master device



Synchronize the data communication on both the SI and SO pins.



The CES is used to select the edge to communicate.



The SBR0~SBR2 is used to determine the baud rate of communication.



The CES, SBR0, SBR1, and SBR2 bits have no effect in Slave mode.



Timing is shown in Figures 6-10a and 6-10b.

 P50//SS:



Slave Select; negative logic.



Generated by a Master device to indicate the Slave(s) has to receive data.



Go low before the first cycle of SCK occurs, and remain low until the last (8th) cycle is

completed



Ignore the data on the SI and SO pins when /SS is high, because SO is no longer driven



Timing is shown in Figures 6-10a and 6-10b.

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