EKTF6708 datasheet(126/158 Pages) EMC

126 / 158 page

eKTF6708

8-Bit Microcontroller

116



IC Product Specification (V1.2) 03.12.2020

(This specification is subject to change without prior notice)

Read

Write

I2CDB reg

I2CSA reg

Start and Stop

bit Detect

SCL

SDA

MSb

LSb

Add Match

FULL

I2CRIF

Buffer Full Detector

Match Detect

I2CDA reg

Control and

Status reg

I2CTIF

Figure 6-11

eKTF6708 I2C Block Diagram

The

eKTF6708 supports a bidirectional, 2-wire bus, 7/10-bit addressing, and data

transmission protocol. A device sending data to the bus is defined as transmitter, while a

device receiving the data is defined as a receiver. The bus has to be controlled by a

Master device which generates the Serial Clock (SCL), controls the bus access, and

generates the Start and Stop conditions. Both Master and Slave can operate as

transmitter or receiver, but the Master device determines which mode is activated.

Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a

pull-up resistor. When the bus is free, both lines are HIGH. The output stages of the

devices connected to the bus must have an open-drain or open-collector to perform the

wired-AND function. Data on the

2C-bus can be transferred at the rates of up to 100

kbit/sec in Standard-mode or up to 400 kbit/sec in Fast-mode.

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or

LOW state of the data line can only be changed when the clock signal on the SCL line is

LOW.

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