PFS154 datasheet(34/91 Pages) PADAUK

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PFS154

8bit MTP Type IO Controller

Page 34 of 91

PDK-DS-PFS154_CN_V105 –Jun. 9, 2020

5.6. Watchdog Timer

The watchdog timer (WDT) is a counter with clock coming from ILRC. WDT can be cleared by power-on-reset

or by command wdreset at any time. There are four different timeout periods of watchdog timer can be chosen

by setting the misc register, it is:

 8k ILRC clock period when misc[1:0]=00 (default)

 16k ILRC clock period when misc[1:0]=01

 64k ILRC clock period when misc[1:0]=10

 256k ILRC clock period when misc[1:0]=11

The frequency of ILRC may drift a lot due to the variation of manufacture, supply voltage and temperature; user

should reserve guard band for safe operation. Besides, the watchdog period will also be shorter than expected

after Reset or Wakeup events. It is suggested to clear WDT by wdreset command after these events to ensure

enough clock periods before WDT timeout.

When WDT is timeout, PFS154 will be reset to restart the program execution. The relative timing diagram of

watchdog timer is shown as Fig. 5.

VDD

Time Out

Program

Execution

tSBP

Watch Dog Time Out Sequence

VDD

Time Out

Program

Execution

tSBP

Watch Dog Time Out Sequence

Fig. 5: Sequence of Watch Dog Time Out

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