USB3347CPTR datasheet(47/92 Pages) MICROCHIP

47 / 92 page

 2009-2018 Microchip Technology Inc.

DS00002646A-page 47

USB334x

6.2.3

ULPI REGISTER READ

A ULPI register read operation is given in Figure 6-5. The Link drives a TX CMD byte with DATA[7:6] = 11h for a register

read. DATA[5:0] of the ULPI TX command bye contain the register address.

At T0, the Link will place the TX CMD on the data bus. At T2, the PHY will bring NXT high, signaling the Link it is ready

to accept the data transfer. At T3, the PHY reads the TX CMD, determines it is a register read, and asserts DIR to gain

control of the bus. The PHY will also de-assert NXT. At T4, the bus ownership has transferred back to the PHY and the

PHY drives the requested register onto the data bus. At T5, the Link will read the data bus and the PHY will drop DIR

low returning control of the bus back to the Link. After the turn around cycle, the Link must drive a ULPI Idle command

at T6.

A ULPI extended register read operation is shown in Figure 6-6.To read an extended register, the Link writes the TX

CMD with the address set to 2Fh. At T2, the PHY will assert NXT, signaling the Link it is ready to accept the extended

address. At T3, the Link places the extended register address on the bus. At T4, the PHY reads the extended address,

and asserts DIR to gain control of the bus. The PHY will also de-assert NXT. At T5, the bus ownership has transferred

back to the PHY and the PHY drives the requested register onto the data bus. At T6, the Link will read the data bus and

the PHY will de-assert DIR returning control of the bus back to the Link. After the turn around cycle, the Link must drive

a ULPI Idle command at T6.

FIGURE 6-5:

ULPI REGISTER READ IN SYNCHRONOUS MODE

DIR

CLK

DATA[7:0]

STP

NXT

TXD CMD

reg read

Idle

Reg Data

Turn around

Idle

USB3347CPTR 데이터시트(PDF) 47 Page - Microchip Technology