7

Register description

The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration and

temperature data. The register addresses, consisting of 7 bits, are used to identify them and to write the data

through the serial interface.

7.1

CTRL_REG1 (20h)

Control register 1

NORM_

MOD_EN

IF_ADD_INC

0 (1)

0(1)

BOOT

SW_RESET

DRDY_

PULSE

BDU

1. This bit must be set to ‘0’ for the correct operation of the device.

NORM_MOD_EN

Normal mode enable. Default value: 0

(0: power down; 1: enabled)

IF_ADD_INC

Register address is automatically incremented during a multiple byte access with SPI serial interface.

Default value: 1

(0: disabled; 1: enabled)

BOOT

Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content(1))

SW_RESET

Software reset. Default value: 0

With SW_RESET the values in the writable CTRL registers are changed to the default values.

(0: normal mode; 1: reset device)

This bit is cleared by hardware at the end of the operation.

DRDY_PULSE

Data-ready on INT1 pin. Default value: 0

(0: DRDY latched; 1: DRDY pulsed, pulse duration is 1/4 ODR)

BDU

Block Data Update. Default value: 0

(0: continuous update; 1: output registers not updated until MSB and LSB read)

1. Boot request is executed as soon as the internal oscillator is turned on. It is possible to set the bit while in power-down

mode, in this case it will be served at the next normal mode.

IIS3DHHC

Register description

DS12292 - Rev 3

page 17/30