LSM6DSRTR datasheet(13/168 Pages) STMICROELECTRONICS

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4.4.2

I²C - inter-IC control interface

Subject to general operating conditions for Vdd and Top.

Table 6. I²C slave timing values

Symbol

Parameter

I²C fast mode(1)(2)

I²C fast mode +(1)(2)

Unit

Min

Max

Min

Max

f(SCL)

SCL clock frequency

400

1000

kHz

tw(SCLL)

SCL clock low time

1.3

0.5

µs

tw(SCLH) SCL clock high time

0.6

0.26

tsu(SDA)

SDA setup time

100

th(SDA)

SDA data hold time

0.9

µs

th(ST)

START/REPEATED START condition hold time

0.6

0.26

tsu(SR)

REPEATED START condition setup time

0.6

0.26

tsu(SP)

STOP condition setup time

0.6

0.26

tw(SP:SR) Bus free time between STOP and START condition

1.3

0.5

Data valid time

0.9

0.45

Data valid acknowledge time

0.9

0.45

Capacitive load for each bus line

400

550

1. Data based on standard I²C protocol requirement, not tested in production.

2. Data for I²C fast mode and I²C fast mode + have been validated by characterization, not tested in production.

Figure 6. I²C slave timing diagram

SDA

SCL

tsu(SP)

tw(SCLL)

tsu(SDA)

tsu(SR)

th(ST)

tw(SCLH)

th(SDA)

tw(SP:SR)

START

REPEATED

START

STOP

START

Note: Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both ports.

LSM6DSR

Communication interface characteristics

DS11976 - Rev 2

page 13/168

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