| 전자부품 데이터시트 검색엔진 |
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UPD16704 데이터시트(PDF) 8 Page - NEC |
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UPD16704 데이터시트(HTML) 8 Page - NEC |
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8 / 14 page ![]() Data Sheet S15809EJ1V0DS 8 µµµµ PD16704 (2/2) Pin Symbol Pin Name Pad No I/O Description VSS Logic ground 30 - 33 – Connect this pin to the ground of the system. VEE1 Negative power supply for internal operation 7 - 10, 39 - 42 – –15 to –5 V VEE2 Driver negative power supply 3 - 6, 43 - 46 – The driver output: low level (VEE2 to VEE1 < 6.0 V) Cautions 1. To prevent latch-up, turn on power to VDD1, VEE1, VEE2, VDD2, and logic input in this order. Turn off power in the reverse order. These power up/down sequence must be observed also during transition period. 2. Insert a capacitor of about 0.1 µµµµF between each power line, as shown below, to secure noise margin such as VIH and VIL. VDD2 VDD1 0.1 F VSS VEE1 VEE2 µ 0.1 F µ 0.1 F µ |
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