RX113 datasheet(28/131 Pages) RENESAS

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R01DS0216EJ0120 Rev.1.20

Page 28 of 131

Sep 07, 2020

RX113 Group

4. I/O Registers

I/O Registers

This section provides information on the on-chip I/O register addresses and bit configuration. The information is given as

shown below. Notes on writing to I/O registers are also given below.

(1)

I/O register addresses (address order)

• Registers are listed from the lower allocation addresses.

• Registers are classified according to module symbols.

• Numbers of cycles for access indicate numbers of cycles of the given base clock.

• Among the internal I/O register area, addresses not listed in the list of registers are reserved. Reserved addresses

must not be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and

subsequent operations cannot be guaranteed.

(2)

Notes on writing to I/O registers

While writing to an I/O register, the CPU starts executing subsequent instructions before the I/O register write access is

completed. This may cause the subsequent instructions to be executed before the write value is reflected in the operation.

The examples below show how subsequent instructions must be executed after a write access to an I/O register is

completed.

[Examples of cases requiring special care]

• The subsequent instruction must be executed while an interrupt request is disabled with the IENj bit in IERn of the

ICU (interrupt request enable bit) set to 0.

• A WAIT instruction is executed immediately after the preprocessing for causing a transition to the low power

consumption state.

In the above cases, after writing to an I/O register, wait until the write operation is completed using the following

procedure and then execute the subsequent instruction.

(a)

Write to an I/O register.

(b)

Read the value in the I/O register and write it to a general register.

(c)

Execute the operation using the value read.

(d)

Execute the subsequent instruction.

Example of instructions

• Byte-size I/O registers

MOV.L #SFR_ADDR, R1

MOV.B #SFR_DATA, [R1]

CMP

[R1].UB, R1

;; Next process

• Word-size I/O registers

MOV.L #SFR_ADDR, R1

MOV.W #SFR_DATA, [R1]

CMP

[R1].W, R1

;; Next process

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