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STM32L552CC 데이터시트(PDF) 60 Page - STMicroelectronics |
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STM32L552CC 데이터시트(HTML) 60 Page - STMicroelectronics |
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60 / 340 page ![]() Functional overview STM32L552xx 60/340 DS12737 Rev 6 • Three functional modes: indirect, status-polling, and memory-mapped • Read and write support in memory-mapped mode • Supports for single, dual, quad and octal communication • Dual-quad mode, where 8 bits can be sent/received simultaneously by accessing two quad memories in parallel. • SDR and DTR support • Data strobe support • Fully programmable opcode for both indirect and memory mapped mode • Fully programmable frame format for both indirect and memory mapped mode • Each of the five following phases can be configured independently (enable, length, single/dual/quad communication) – Instruction phase – Address phase – Alternate bytes phase – Dummy cycles phase – Data phase • HyperBusTM support • Integrated FIFO for reception and transmission • 8, 16, and 32-bit data accesses are allowed • DMA channel for indirect mode operations • Timeout management • Interrupt generation on FIFO threshold, timeout, status match, operation complete, and access error TrustZone security When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset. Up to two non-secure area can be configured thought the TZSC MPCWM1 controller with a granularity of 64 Kbytes. The OCTOSPI registers can be configured as secure through the TZSC controller. |
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