STM32WLE4JC datasheet(113/145 Pages) STMICROELECTRONICS

113 / 145 page

DS13105 Rev 8

113/145

STM32WLE5/E4xx

Electrical characteristics

133

Figure 21. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in the above table.

Otherwise the reset is not be taken into account by the device.

3. The external capacitor on NRST must be placed as close as possible to the device.

5.3.18

Analog switches booster

Table 75. NRST pin characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL(NRST) NRST input low level voltage

0.3 x VDD

VIH(NRST) NRST input high level voltage

0.7 x VDD

Vhys(NRST) NRST Schmitt trigger voltage hysteresis

200

RPU

Weak pull-up equivalent resistor(2)

VIN = VSS

kΩ

VF(NRST) NRST input, filtered pulse

VNF(NRST) NRST input, not filtered pulse

1.8 V ≤ VDD ≤ 3.6 V

350

Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series

resistance is minimal (~10 %)

MS19878V3

RPU

VDD

Internal reset

External

reset circuit

(1)

NRST

(2)

Filter

0.1 μF

Table 76. Analog switches booster characteristics(1)

Symbol

Parameter

Min

Typ

Max

Unit

VDD

Supply voltage

1.8

3.6

tSU(BOOST) Booster startup time

240

µs

IDD(BOOST)

Booster consumption for 1.8 V ≤ VDD ≤ 2.0 V

250

µA

Booster consumption for 2.0 V ≤ VDD ≤ 2.7 V

500

Booster consumption for 2.7 V ≤ VDD ≤ 3.6 V

900

1. Guaranteed by design.

STM32WLE4JC 데이터시트(PDF) 113 Page - STMicroelectronics

STM32WLE4JC 데이터시트(HTML) 113 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL