STM32WLE4JC datasheet(17/145 Pages) STMICROELECTRONICS

17 / 145 page

DS13105 Rev 8

17/145

STM32WLE5/E4xx

Functional overview

•

Write protection (WRP): the protected area is protected against erasing and

programming. Two areas can be selected, with 4-Kbyte granularity.

•

Proprietary code readout protection (PCROP): two parts of the Flash memory can be

protected against read and write from third parties. The protected area is execute-only:

it can only be reached by the STM32 CPU, as an instruction code, while all other

accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.

Two areas can be selected, with 2-Kbyte granularity. An additional option bit

(PCROP_RDP) is used to select if the PCROP area is erased or not when the RDP

protection is changed from Level 1 to Level 0.

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

•

single error detection and correction

•

double error detection

•

address of the ECC fail can be read in the FLASH_ECCR register

3.5.2

Embedded SRAM

The devices feature up to 64 Kbytes of embedded SRAM, split in two blocks:

•

SRAM1: up to 32 Kbytes mapped at address 0x2000 0000

•

SRAM2: up to 32 Kbytes located at address 0x2000 8000 (contiguous to SRAM1), also

mirrored at 0x1000 0000, with hardware parity check (this SRAM can be retained in

Standby mode)

The SRAMs can be accessed in read/write with 0 wait states for all CPU clock speeds.

Backup registers

1Yes

Yes

NA(2)

Yes

NANANANA

SRAM2

Yes

Yes(2)

No(2)

Yes

1. The option byte can be modified by the sub-GHz radio.

2. Erased when RDP changes from Level 1 to Level 0.

Table 3. Access status versus RDP level and execution mode (continued)

Area

RDP

level

User execution

Debug, boot from SRAM or boot from

system memory (loader)

Read

Write

Erase

Read

Write

Erase

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