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STPMIC1 데이터시트(PDF) 84 Page - STMicroelectronics |
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STPMIC1 데이터시트(HTML) 84 Page - STMicroelectronics |
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84 / 140 page ![]() 6.3.10 Watchdog control register (WDG_CR) Table 34. WDG_CR 7 6 5 4 3 2 1 0 reserved reserved reserved reserved reserved reserved WDG_RST WDG_ENA R/W R/W R/W R/W R/W R/W R/W R/W Address: 0x1B Type: read/write register Default: 0x00 Description: watchdog control register [7 :2] Reserved [1] WDG_RST: watchdog counter reset 0: NA 1: Watchdog downcounter is reloaded with a value in WDG_TIMER_CR (self-cleared bit) [0] WDG_ENA: watchdog enable bit 0: watchdog is disabled 1: watchdog is enabled STPMIC1 Control registers DS12792 - Rev 7 page 84/140 |
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