MC56F81663 datasheet(14/73 Pages) NXP

14 / 73 page

EOnCE 56800EX CPU

Program Bus

Core Data Bus

Secondary Data Bus

Program/Data Flash

Up to 128 KB

Data/Program RAM

Up to 20 KB

Interrupt Controller

QSCI

0,1

QSPI

LPI2C

0,1

Quad Timer

4ch

eFlexPWM

NanoEdge

ADCA

12Bit

ADCB

12Bit

Compartors With

8bit DAC A,B,C,D

Watchdog (COP)

EWM

CRC

DAC

12Bit

Event

Generator

Inter-Module

Crossbar

Inter Module connection

GPIO & Peripheral MUX

Crystal OSC

Internal IRC

2 MHz/ 8 MHz

Internal IRC

200 kHz

PLL

Power Management

Controller (PMC)

System Integration

Module (SIM)

Package

Pins

Peripheral Bus

JTAG

Inter Module Crossbar Inputs

Inter Module Crossbar Outputs

Program

Controller

(PC)

Address

Generation

Unit (AGU)

Arithmetic

Logic Unit

(ALU)

Bit

Manipulation

Unit

Inter Module Crossbar Outputs

Inter Module Crossbar Inputs

Op-Amp

0.1

Boot ROM

32 KB

eDMA Controller

Periodic Interrupt

Timer (PIT32) 0,1

Quadrature

Decoder

ROM Patch

Controller

Figure 1. System block diagram

Clock sources

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

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