MC56F81663 datasheet(39/73 Pages) NXP

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9.3 ESD handling ratings

Although damage from electrostatic discharge (ESD) is much less common on these

devices than on early CMOS circuits, use normal handling precautions to avoid exposure

to static discharge. Qualification tests are performed to ensure that these devices can

withstand exposure to reasonable levels of static without suffering any permanent

damage.

A device is defined as a failure if after exposure to ESD pulses, the device no longer

meets the device specification. Complete DC parametric and functional testing is

performed as per the applicable device specification at room temperature followed by hot

temperature, unless specified otherwise in the device specification.

Table 5. ESD/Latch-up Protection

Characteristic1

Min

Max

Unit

Notes

ESD for Human Body Model (VHBM)

–2000

+2000

ESD for Charge Device Model (VCDM)

–500

+500

Latch-up current at TA= 85°C (ILAT) (V part)

–100

+100

1. Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions

unless otherwise noted.

2. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM).

3. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

4. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

9.4 Voltage and current operating ratings

Table 6. Voltage and current operating ratings

Symbol

Description

Min.

Max.

Unit

VDD

Digital supply voltage

–0.3

3.8

IDD

Digital supply current

—

120

VIO

IO pin input voltage

–0.3

VDD + 0.3

Instantaneous maximum current single pin limit (applies to all

port pins)

–25

VDDA

Analog supply voltage

VDD – 0.3

VDD + 0.3

10 General

General

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

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