ADAV803ASTZ datasheet(51/56 Pages) AD

51 / 56 page

ADAV803

Rev. 0 | Page 51 of 56

egister 1

ACLK1

ACLK0

Table 75. Internal Clocking Control R

DCLK2

CLK1

D LK0

LK2

CLK2

ICLK2

ADDRESS = 1110110 (0x76)

DCLK2–0

DAC clock source select.

000 = XIN.

LINT2.

LL (512 × fS).

101 = DIR PLL (256 × fS).

XIN.

C clock source select.

IN.

r for internal clock ICLK2.

001 = MCLK

010 = PLLINT1.

011 = PL

100 = DIR P

110 = XIN.

111 =

ACLK2–0

000 = X

001 = MCLKI.

010 = PLLINT

011 = PLLINT2.

100 = DIR PLL (512 × fS).

101 = DIR PLL (256 × fS).

110 = XIN.

111 = XIN.

ICLK2_1–0

Source selecto

00 = XIN.

01 = MCLKI.

10 = PLLINT1.

11 = PLLINT2.

Table 76. Internal Clo

l Register 2

RES

ICLK1_1

ICLK1_0

PLL2INT1

PLL2INT0

PLL1INT

cking Contro

RES

ADDRESS = 1110111 (0x77)

ICLK1_1–0

Source selector for internal clock ICLK1.

00 = XIN.

01 = MCLKI.

10 = PLLINT1.

11 = PLLINT2.

PLL2INT1–0

PLL2 internal selector (see Figure 38).

00 = FS2.

01 = FS2/2.

10 = FS3.

11 = FS3/2.

PLL1INT

PLL1 internal selector.

0 = FS1.

1 = FS1/2.

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