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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADAV803ASTZ 데이터시트(PDF) 6 Page - Analog Devices |
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ADAV803ASTZ 데이터시트(HTML) 6 Page - Analog Devices |
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6 / 56 page  ADAV803 Rev. 0 | Page 6 of 56 Parameter Min Typ Max Unit Comments Power-Down Current RESET low, no MCLK Analog Current 18 mA Digital Current 2.5 mA Digital Interface Current 700 µA DIRIN/DIROUT Current 3.5 mA PLL Current 900 µA Power Supply Rejection Signal at Analog Supply Pins −70 dB 1 kHz, 300 mV p-p −70 dB 20 kHz, 300 mV p-p 1 Guaranteed by design. TIMING SPECIFICATIONS Timing specifications are guaranteed over the full temperature and supply range. Table 3. Parameter Min Typ Max Unit Comments MASTER CLOCK AND RESET fMCLK MCLKI Frequency 12.288 54 MHz fXIN XIN Frequency 27 54 MHz tRESET RESET Low 20 ns I2C PORT fSCL SCL Clock Frequency 400 kHz tSCLH SCL High 0.6 µs tSCLL SCL Low 1.3 µs Start Condition tSCS Setup Time 0.6 µs Relevant for repeated start condition tSCH Hold Time 0.6 µs After this period, the first clock is generated tDS Data Setup Time 100 ns tSCR SCL Rise Time 300 ns tSCF SCL Fall Time 300 ns tSDR SDA Rise Time 300 ns tSDF SDA Fall Time 300 ns Stop Condition tSCS Setup Time 0.6 µs SERIAL PORTS1 Slave Mode tSBH xBCLK High 40 ns tSBL xBCLK Low 40 ns fSBF xBCLK Frequency 64 × fS tSLS xLRCLK Setup 10 ns To xBCLK rising edge tSLH xLRCLK Hold 10 ns From xBCLK rising edge tSDS xSDATA Setup 10 ns To xBCLK rising edge tSDH xSDATA Hold 10 ns From xBCLK rising edge tSDD xSDATA Delay 10 ns From xBCLK falling edge |
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