HM24C32/HM24C64

6

DETAILED OPERATING INFORMATION

I²C DATA BUS AND TRANSMISSION PROTOCOL

I²C-Bus Interface

The HM24CXX supports I²C-bus transmission protocol. The I²C-bus is a bidirectional, two-line

communication interface. The two lines are a serial data line (SDA) and a serial clock line (SCL).

Both lines must be connected to a positive supply via a pull-up resistor. A typical bus

configuration using this 2-wire protocol is show in Figure 4.

Figure 4. Typical 2-Wire Bus Configuration

A device that sends data onto the bus is defined as a transmitter and a device receiving data as

a receiver. The device that controls the message is called a master. The devices that are

controlled by the master are referred to as slaves. The master device generates the serial clock

(SCL), controls the bus access, and generates the START and STOP conditions. The

HM24CXX operates as a slave on the I²C-bus.

Data transfer may be initiated only when the bus is not busy (Both data and clock lines remain

HIGH). Each data transfer is initiated with a START condition and terminated with a STOP

condition. The number of data bytes transferred between START and STOP conditions is not

limited, and is determined by the master device. The information is transferred byte-wise and

each receiver acknowledges with a ninth bit.

Start and Stop Conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of

the data line, while the clock is HIGH is defined as the START condition(S). A LOW-to-HIGH

transition of the data line while the clock is HIGH is defined as the STOP condition (P), see

Figure 5.

Figure 5. Definition of Start and Stop Condition

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