PSD813F1AV-12MIT datasheet(60/110 Pages) STMICROELECTRONICS

60 / 110 page

PSD813F1V

60/110

Enable Out

The Enable Out register can be read by the micro-

controller. It contains the output enable values for

a given port. A ‘1’ indicates the driver is in output

mode. A ‘0’ indicates the driver is in tri-state and

the pin is in input mode.

Ports A and B – Functionality and Structure

Ports A and B have similar functionality and struc-

ture, as shown in Figure 29. The two ports can be

configured to perform one or more of the following

functions:

■

MCU I/O Mode

■

CPLD Output – Macrocells McellAB7-

McellAB0 can be connected to Port A or Port

B. McellBC7-McellBC0 can be connected to

Port B or Port C.

■

CPLD Input – Via the Input Macrocells (IMC).

■

Latched Address output – Provide latched

address output as per Table 21., page 55.

■

Address In – Additional high address inputs

using the Input Macrocells (IMC).

■

Open Drain/Slew Rate – pins PA3-PA0 and

PB3-PB0 can be configured to fast slew rate,

pins PA7-PA4 and PB7-PB4 can be

configured to Open Drain Mode.

■

Data Port – Port A to D7-D0 for 8 bit non-

multiplexed bus

■

Multiplexed Address/Data port for certain

types of MCU bus interfaces.

■

Peripheral Mode – Port A only

Figure 29. Port A and Port B Structure

DATA OUT

REG.

ADDRESS

MACROCELL OUTPUTS

ENABLE PRODUCT TERM (.OE)

ALE

READ MUX

CPLD - INPUT

CONTROL REG.

DIR REG.

INPUT

MACROCELL

ENABLE OUT

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT

A OR B PIN

DATA OUT

ADDRESS

A[ 7:0] OR A[15:8]

AI02887

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