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PSD813F1AV-12MIT 데이터시트(PDF) 99 Page - STMicroelectronics

부품명 PSD813F1AV-12MIT
상세설명  Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 3.3V
PDF  110 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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PSD813F1AV-12MIT 데이터시트(HTML) 99 Page - STMicroelectronics

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PSD813F1V
Table 72. ISC Timing (3V devices)
Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.
Table 73. Power-down Timing (5V devices)
Note: 1. tCLCL is the period of CLKIN (PD1).
Table 74. Power-down Timing (3V devices)
Note: 1. tCLCL is the period of CLKIN (PD1).
Symbol
Parameter
Conditions
-15
-20
Unit
MinMax
MinMax
tISCCF
Clock (TCK, PC1) Frequency (except for
PLD)
(Note 1)
10
9
MHz
tISCCH
Clock (TCK, PC1) High Time (except for PLD)
(Note 1)
45
51
ns
tISCCL
Clock (TCK, PC1) Low Time (except for PLD)
(Note 1)
45
51
ns
tISCCFP
Clock (TCK, PC1) Frequency (PLD only)
(Note 2)
22
MHz
tISCCHP
Clock (TCK, PC1) High Time (PLD only)
(Note 2)
240
240
ns
tISCCLP
Clock (TCK, PC1) Low Time (PLD only)
(Note 2)
240
240
ns
tISCPSU
ISC Port Set Up Time
13
15
ns
tISCPH
ISC Port Hold Up Time
10
10
ns
tISCPCO
ISC Port Clock to Output
36
40
ns
tISCPZV
ISC Port High-Impedance to Valid Output
36
40
ns
tISCPVZ
ISC Port Valid Output to
High-Impedance
36
40
ns
Symbol
Parameter
Conditions
-90
-12
-15
Unit
Min
Max
Min
Max
Min
Max
tLVDV
ALE Access Time from Power-down
90
120
150
ns
tCLWH
Maximum Delay from
APD Enable to Internal PDN Valid
Signal
Using CLKIN
(PD1)
15 * tCLCL
1
µs
Symbol
Parameter
Conditions
-15
-20
Unit
Min
Max
Min
Max
tLVDV
ALE Access Time from Power-down
150
200
ns
tCLWH
Maximum Delay from APD Enable to
Internal PDN Valid Signal
Using CLKIN
(PD1)
15 * tCLCL
1
µs



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