ADRF6720ACPZ-R7 datasheet(22/44 Pages) AD

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ADRF6720

Data Sheet

SERIAL PORT INTERFACE

The SPI of the ADRF6720 allows the user to configure the

device for specific functions or operations via a 3-pin SPI port.

This interface provides users with added flexibility and

customization. The SPI consists of three control lines: SCLK,

SDIO, and CS. The timing requirements for the SPI port are

shown in Table 2.

The ADRF6720 protocol consists of seven register address bits,

followed by a read/write and 16 data bits. Both the address and

data fields are organized with the most significant bit (MSB)

first, and end with the least significant bit (LSB).

On a write cycle, up to 16 bits of serial write data are shifted in,

MSB to LSB. If the rising edge of CS occurs before the LSB of

the serial data is latched, only the bits that were latched are

written to the device. If more than 16 data bits are shifted in, the

16 most recent bits are written to the device. The ADRF6720

input logic level for the write cycle supports an interface as low

as 1.4 V.

On a read cycle, up to 16 bits of serial read data are shifted out,

MSB first. Data shifted out beyond 16 bits is undefined.

Readback content at a given register address does not

necessarily correspond with the write data of the same address.

The output logic level for a read cycle is 2.3 V.

Rev. 0 | Page 22 of 44

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