ADRF6755ACPZ-R7 datasheet(29/48 Pages) AD

29 / 48 page

Data Sheet

ADRF6755

Rev. B | Page 29 of 48

PROGRAM MODES

The ADRF6755 has 34 8-bit registers to allow program control

of a number of functions. Either an SPI or an I2C interface can

be used to program the register set. For details about the interfaces

and timing, see Figure 63 to Figure 69. The registers are

documented in Table 8 to Table 28.

Several settings in the ADRF6755 are double-buffered. These

settings include the FRAC value, the INT value, the 5-bit R-divider

value, the reference frequency doubler, the R/2 divider, the RFDIV

value, and the charge pump current setting. This means that

two events must occur before the part uses a new value for any

of the double-buffered settings. First, the new value is latched

into the device by writing to the appropriate register. Next, a

new write must be performed on Register CR0. When

For example, updating the fractional value involves a write to

and Register CR1, and, finally, Register CR0. The new acquisition

begins after the write to Register CR0. Double buffering ensures

that the bits written to do not take effect until after the write to

12-Bit Integer Value

of the feedback division factor (N); see Equation 5 for details.

The INT value is a 12-bit number whose MSBs are programmed

through Register CR7, Bits[3:0]. The LSBs are programmed

through Register CR6, Bits[7:0]. The LO frequency setting is

described by Equation 2. An alternative to this equation is

provided by Equation 4, which details how to set the N-divider

value. Note that these registers are double buffered.

25-Bit Fractional Value

of the feedback division factor (N); see Equation 5 for details.

The FRAC value is a 25-bit number whose MSB is programmed

through Register CR3, Bit 0. The LSB is programmed through

Equation 2. An alternative to this equation is described by

Equation 4, which details how to set the N-divider value. Note

that these registers are double buffered.

RFDIV Value

The RFDIV value is dependent on the value of the LO frequency.

The RFDIV value can be selected from the list in Table 6. Apply

the selected RFDIV value to Equation 4, together with the LO

frequency and PFD frequency values, to calculate the correct

N-divider value.

Reference Input Path

The reference input path consists of a reference frequency doubler,

a 5-bit reference divider, and a divide-by-2 function (see Figure 53).

The doubler is programmed through Register CR10, Bit 5. The

5-bit divider and divide-by-2 are enabled by programming

Charge Pump Current

With an RSET value of 4.7 kΩ, the maximum charge pump current is

5 mA. The following equation applies:

ICPmax = 23.5/RSET

The charge pump current has 16 settings from 312.5 μA to 5 mA.

For the loop filter that is specified in the application solution, a

charge pump current of 5 mA (Register CR9[7:4] = 0xF) gives a

loop bandwidth of 100 kHz, which is the recommended loop

bandwidth setting.

Transmit Disable Control (TXDIS)

The transmit disable control (TXDIS) is used to disable the RF out-

put. TXDIS is normally held low. When asserted (brought high), it

disables the RF output. Register CR14 is used to control which

circuit blocks are powered down when TXDIS is asserted. To meet

both the off isolation power specifications and the turn-on/

turn-off settling time specifications, a value of 0x80 should be

loaded into Register CR14. This effectively ensures that the

attenuator is always enabled when TXDIS is asserted, even if other

circuitry is disabled.

Power-Down/Power-Up Control Bits

The four programmable power-up and power-down control bits

are as follows:



including the VCO. This bit is normally set to a default value

of 0 to power up the PLL.



normally set to a default value of 0 to power up the

RFDIVIDER.



LOMON and LOMON. The default is 0 when the monitor

outputs are powered down. Setting this bit to 1 powers

up the monitor outputs to one of four options, −6 dBm,

−12 dBm, −18 dBm, or −24 dBm, as controlled by



power. The default is 0, which powers down the modulator.

Write a 1 to this bit to power up the modulator.

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