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ADRF6755ACPZ-R7 데이터시트(PDF) 36 Page - Analog Devices

부품명 ADRF6755ACPZ-R7
상세설명  100 MHz to 2400 MHz I/Q Modulator with Integrated Fractional-N PLL and VCO
PDF  48 Pages
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ADRF6755ACPZ-R7 데이터시트(HTML) 36 Page - Analog Devices

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ADRF6755
Data Sheet
Rev. B | Page 36 of 48
To change the LO frequency to 925 MHz,
•
fPFD = 40 MHz (assumed)
•
Divide ratio N = 46.25; therefore, INT = 46 decimal and
FRAC = 8,388,608
•
RFDIVIDER = divide-by-2. See Table 6.
Register CR28[2:0] = 001
Register CR27[4] = 0
The INT registers contain the following values:
Register CR7 = 0x00 and Register CR6 = 0x2E
The FRAC registers contain the following values:
Register CR3 = 0x04, Register CR2 = 0x80,
Register CR1 = 0x00, and Register CR0 = 0x00
Note that Register CR27 should be the last write in this
sequence, preceded by CR0. Writing to Register CR0 causes all
double-buffered registers to be updated, including the INT,
FRAC, and RFDIV registers, and starts a new PLL acquisition.



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