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ADRF6821 데이터시트(PDF) 48 Page - Analog Devices

부품명 ADRF6821
상세설명  450 MHz to 2800 MHz, DPD RFIC with Integrated Fractional-N PLL and VCO
PDF  61 Pages
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ADRF6821 데이터시트(HTML) 48 Page - Analog Devices

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ADRF6821
Data Sheet
Rev. A | Page 48 of 61
Address: 0x1201, Reset: 0x01, Name: INT_H
Integer-N Word - Optionally Double
Buffered.
0
1
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] INT_DIV[15:8] (R/W)
Table 49. Bit Descriptions for INT_H
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
INT_DIV,
Bits[15:8]
Integer-N Word—Optionally Double Buffered. Writing the LSB
of the integer word normally causes an autotune event.
0x189
R/W
Address: 0x1202, Reset: 0x00, Name: FRAC1_L
FRAC- N Wor d - Optionally Double Buffer ed
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[ 7 : 0 ] FRAC[ 7 : 0 ] ( R/W )
Table 50. Bit Descriptions for FRAC1_L
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
FRAC, Bits[7:0]
FRAC-N Word – Optionally Double Buffered. Lower 8 bits of 24-bit FRAC value.
0x0
R/W
Address: 0x1203, Reset: 0x00, Name: FRAC1_M
FRAC- N Wor d - Optionally Double Buffer ed
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[ 7 : 0 ] FRAC[ 1 5 : 8 ] ( R/W )
Table 51. Bit Descriptions for FRAC1_M
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
FRAC, Bits[15:8]
FRAC-N Word – Optionally Double Buffered. Lower 8 bits of 24-bit FRAC value.
0x0
R/W
Address: 0x1204, Reset: 0x00, Name: FRAC1_H
FRAC- N Wor d - Optionally Double Buffer ed
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[ 7 : 0 ] FRAC[ 2 3 : 1 6 ] ( R/W )
Table 52. Bit Descriptions for FRAC1_H
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
FRAC, Bits[23:16]
FRAC-N Word – Optionally Double Buffered. Lower 8 bits of 24-Bit FRAC value.
0x0
R/W



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