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ADRF6821 데이터시트(PDF) 8 Page - Analog Devices

부품명 ADRF6821
상세설명  450 MHz to 2800 MHz, DPD RFIC with Integrated Fractional-N PLL and VCO
PDF  61 Pages
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ADRF6821 데이터시트(HTML) 8 Page - Analog Devices

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ADRF6821
Data Sheet
Rev. A | Page 8 of 61
SERIAL PERIPHERAL INTERFACE (SPI) TIMING SPECIFICATIONS
Table 6.
Parameter
Symbol
Min
Typ
Max
Unit
TIMING REQUIREMENTS
SDI to SCLK Rising Edge Setup
tDS
8
ns
SCLK Rising Edge to SDI Hold
tDH
8
ns
Period of SCLK
tCLK
50
ns
CS Falling Edge to SCLK Rising Edge, Setup Time
tS
10
ns
SCLK Rising Edge to CS Rising Edge, Hold Time
tC
30
ns
SCLK Falling Edge to Valid Readback Data, SDIO or SDO (Not Shown in Figure 2)
tDV
18
ns
SCLK
Period of SCLK for a Logic High State
tHIGH
25
ns
Period of SCLK for a Logic Low State
tLOW
25
ns
SPI Timing Diagram
DON’T CARE
DON’T CARE
SCLK
SDIO
R/W
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON’T CARE
DON’T CARE
CS
tS
tDS
tHIGH
tDH
tLOW
tCLK
tC
Figure 2. SPI Write (MSB First), 16-Bit Instruction, Timing Measurements



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