ACE25AB400G

Serial NOR Flash Memory 4M bits 3.0V Dual I/O Serial Flash Memory with 4KB Uniform Sector

VER 1.1

27

Enable Reset (66H) and Reset (99H)

If the Reset command is accepted, any on-going internal operation will be terminated and the device will

return to its default power-on state and lose all the current volatile settings, such as Volatile Status

Register bits, Write Enable Latch status (WEL).

The “Reset (99H)” command sequence as follow: CS# goes low→Sending Enable Reset command→

CS# goes high→CS# goes low→Sending Reset command→CS# goes high. Once the Reset command is

accepted by the device, the device will take approximately tRSTR to reset. During this period, no

command will be accepted.

Continuous Read Mode Reset (CRMR) (FFH)

The Dual I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to further re-

duce command overhead. By setting the (M7-0) to AXH, the next Dual I/O Fast Read operations do not

require the BBH command code.

Because the ACE25AB400G has no hardware reset pin, so if Continuous Read Mode bits are set to

“AXH”, the ACE25AB400G will not recognize any standard SPI commands. So Continuous Read Mode

Reset command will re- lease the Continuous Read Mode from the “AXH” state and allow standard SPI

command to be recognized. The command sequence is shown in Figure 26.

Figure25. Enable Reset and Reset command Sequence Diagram

Figure26. Continuous Read Mode Reset Sequence Diagram