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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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VSC880TY 데이터시트(PDF) 21 Page - Vitesse Semiconductor Corporation |
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VSC880TY 데이터시트(HTML) 21 Page - Vitesse Semiconductor Corporation |
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21 / 28 page  VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC880 High Performance 16x16 Serial Crosspoint Switch G52191-0, Rev 4.2 Page 21 01/05/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com Internet: www.vitesse.com Table 3: Receive Data Output Timing Table Figure 11: CPU Interface Write Cycle Timing Figure 12: CPU Interface Read Cycle Timing Table 4: CPU Interface Timing Table Parameter Description Min Typ Max Units TINT Interrupt pulse width 15 ns TRESET RESET, RESYNEN pulse width 64 ns Parameter Description Min Typ Max Units TOK CSEL falling edge to valid address 5 ns TD CSEL inactive between read cycles 10 ns TSU CWEN valid to CSEL falling edge 5 ns TH CSEL active to CWEN change 5 ns TWV Valid data and address during a write 45 ns TWS CSEL low time during a write 20 ns TWC CSEL cycle time during a write 55 ns TRV CSEL active to valid data 15 45 ns TRZ CSEL deactivate to high impedance data 5 ns TRD CSEL active to low impedance data 0 ns ADDR[5:0] CWEN CDATA[7:0] CSEL Valid Data Valid Address TOK TWV TWC TH TWS TSU ADDR[5:0] CWEN CDATA[7:0] CSEL Valid Data Valid Address Hi-Z TSU TD TH TA TRZ TRD TRV Hi-Z |
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