MPF7100BVMA2ES datasheet(30/125 Pages) NXP

부품명	MPF7100BVMA2ES

상세설명	7-channel power management integrated circuit for high performance applications

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NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 9 March 2021

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Table 21. Power down counter delay

OTP bits

OTP_GRPx_DLY[1:0]

Functional bits

GRPx_DLY[1:0]

Power down delay

(µs)

120

250

500

1000

If RESETBMCU is required to be asserted first before any of the external regulators from

the corresponding group, the RESETBMCU_DLY provides a selectable delay to disable

the regulators after RESETBMCU is asserted.

Table 22. Programmable delay after RESETBMCU is asserted

OTP bits

OTP_RESETBMCU_DLY[1:0]

Functional bits

RESETBMCU_DLY[1:0]

RESETBMCU delay

(µs)

No delay

100

500

If RESETBMCU_DLY is set to 0x00, all regulators in the same power down group as

RESETBMCU is disabled at the same time RESETBMCU is asserted.

Figure 11 shows an example of the power down sequence when PWRDWN_MODE = 1.

MPF7100BVMA2ES 데이터시트(PDF) 30 Page - NXP Semiconductors