24CS512 datasheet(13/66 Pages) MICROCHIP

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DS20005769C-page 13

24CS512

4.0

FUNCTIONAL DESCRIPTION

The 24CS512 supports a bidirectional two-wire bus

and data transmission protocol. A device that sends

data onto the bus is defined as a transmitter and a

device receiving data as a receiver. The bus must be

controlled by a host device which generates the

Serial Clock (SCL), controls the bus access and

generates the Start and Stop conditions, while the

24CS512 works as a client. Both host and client can

operate as a transmitter or receiver, but the host

determines which mode is activated.

5.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line, while the clock line is high, will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 5-1).

5.1

Bus Not Busy (A)

Both data and clock lines remain high.

5.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

5.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must end with a Stop condition.

5.4

Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one bit of data per

clock pulse.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the host device.

5.5

Acknowledge

Each receiving device, when addressed, is obliged to

generate an Acknowledge (ACK) signal after the recep-

tion of each byte. The host device must generate an

extra clock pulse, which is associated with this

Acknowledge bit. See Figure 5-2 for Acknowledge

timing.

A device that acknowledges must pull down the SDA

line during the Acknowledge clock pulse in such a way

that the SDA line is stable low during the high period of

the Acknowledge related clock pulse. Of course, setup

and hold times must be taken into account. During read

operations, the host must signal an end of data to the

client by NOT generating an Acknowledge (NACK) bit

on the last byte that has been clocked out of the client.

In this case, the client (24CS512) will leave the data

line high to enable the host to generate the Stop

condition.

FIGURE 5-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note:

The 24CS512 does not generate any

Acknowledge bits if an internal write cycle

is in progress.

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

Start

Condition

SCL

SDA

(A)

(B)

(D)

(C)

(A)

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