Figure 7-2. Page Write

SCL

SDA

Start

by

Host

ACK

from

Client

ACK

from

Client

Device Address Byte

Word Address Byte

MSb

MSb

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

0

1

0

#

#

#

0

0

ACK

from

Client

Stop

by

Host

ACK

from

Client

Data Word (n)

Data Word (n+x), max of 8 without rollover

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

MSb

MSb

A7 A6 A5

A4

A3 A2 A1

A0

0

D7 D6 D5 D4 D3 D2 D1 D0

0 D7 D6 D5 D4 D3 D2 D1 D0 0

(1)

Notes: 

1.

The A7 bit falls outside of the addressable 1K range and is therefore a don’t care value on an AT24CSW01x.

2.

# indicates the Hardware Address value which is managed by the ordering code of the device (see Table 6-2).

7.3

Acknowledge Polling

An Acknowledge Polling routine can be implemented to optimize time-sensitive applications that would prefer not to

Serial EEPROM write cycle has completed, so a subsequent operation can be started.

Once the internally self-timed write cycle has started, an Acknowledge Polling routine can be initiated. This involves

repeatedly sending a Start condition followed by a valid device address byte with the R/W bit set at logic ‘0’. The

device will not respond with an ACK while the write cycle is ongoing. Once the internal write cycle has completed, the

EEPROM will respond with an ACK, allowing a new read or write operation to be immediately initiated. A flowchart

has been included below in Figure 7-3 to better illustrate this technique.

Figure 7-3. Acknowledge Polling Flowchart

Did

the device

ACK?

Send any

Write

protocol.

Send

Stop

condition

to initiate the

Write cycle.

Send Start

condition followed

by a valid

Device Address

byte with R/W = 0.

Proceed to

next Read or

Write operation.

NO

YES

7.4

Write Cycle Timing

the internal write cycle to the Start condition of the first device address byte sent to the AT24CSW01X/AT24CSW02X

that it subsequently responds to with an ACK. Figure 7-4 has been included to show this measurement. During the

internally self-timed write cycle, any attempts to read from or write to the memory array will not be processed.

AT24CSW01X/AT24CSW02X

Write Operations

and its subsidiaries

Datasheet

DS20006396B-page 19