8.4

Reading the Write Protection Register

To read the contents of the WPR, a random read operation must be sent to the device (see Random Read) so that

the reserved word address bits A7 and A6 can properly be set. It is not possible to read the contents of the WPR with

a current address read.

When reading the WPR contents, data bit 7 through 4 will always read as a logic ‘0’ as seen in Table 8-4.

Figure 8-3. Read Write Protection Register

SCL

SDA

Start

by

Host

Device Address Byte

Word Address Byte

MSb

MSb

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

0

1

1

#

0

0

Dummy Write

Start

by

Host

Device Address Byte

WPR Contents

Stop

by

Host

MSb

MSb

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

0

1

1

#

1

0

0

0

0

0

D3

D2 D1 D0

1

1

1

X

X

X

X

X

X

0

ACK

from

Client

ACK

from

Client

ACK

from

Client

NACK

from

Host

Notes: 

1.

For the AT24CSW04X, the @ indicates the A1 address bit which is managed by the ordering code of the

device (see Table 6-3). For the AT24CSW08X, the @ indicates the A9 address bit.

2.

# indicates the hardware address value which is managed by the ordering code of the device (see Table 6-3

and Table 6-4).

AT24CSW04X/AT24CSW08X

Write Protection

and its subsidiaries

Datasheet

DS20006426B-page 25