AT25DF641A datasheet(57/58 Pages) DIALOG

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AT25DF641A [DATASHEET]

8793F–DFLASH–11/2017

18.

Revision History

Doc. Rev.

Date

Comments

8693F

11/2017

Added patent information.

8693E

8/2017

Updated corporate address.

8693D

5/2013

Updated copyright date, registered logo trademarks and revision dates.

8693C

11/2012

Update to Adesto.

8693B

05/2012

Increase Page Program typical time from 1.0ms to 2.5ms and maximum time from 3ms to 6ms.

Increase Block Erase 64KB typical time from 400ms to 600ms and maximum time from

950ms to 1100ms.

Decrease Read Array 03h maximum clock frequency from 50MHz to 40MHz.

Decrease Dual-Output Read Array 3Bh maximum clock frequency from 85MHz to 65MHz.

Increase Deep Power-Down current maximum from 10µA to 20µA.

Increase active curent, read operation:

• 100MHz from typical 12mA to 30mA and maximum 19mA to 40mA.

• 85MHz from typical 10mA to 29mA and maximum 17mA to 38mA.

• 66MHz from typical 8mA to 28mA and maximum 14mA to 37mA.

• 50MHz from typical 7mA to 27mA and maximum 12mA to 36mA.

• 33MHz from typical 6mA to 26mA and maximum 10mA to 35mA.

• 20MHz from typical 5mA to 25mA and maximum 8mA to 34mA.

Increase maximum tRDPD time from 30µs to 50µs.

Increase Byte Program typical time from 7µs to 30µs.

Increase Chip Erase typical time from 55 sec to 70 sec and maximum from 100 sec to 150 sec.

Add note and two examples to Byte/Page Program section.

Various typographical edits throughout document.

Change from preliminary to complete/released status.

Update template.

8693A

08/2010

Initial document release.

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