AT25SF641 datasheet(32/76 Pages) DIALOG

부품명	AT25SF641

상세설명	64-Mbit, 2.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

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32 / 76 page

AT25SF641

DS-25SF641–111E–3/2018

number of clocks cannot exceed the remaining page length. If more than 256 bytes are sent to the device the addressing

will wrap to the beginning of the page and overwrite previously sent data

The CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Page

Program instruction will not be executed. After CS is driven high, the self-timed Page Program instruction will

commence for a time duration of tPP (See Section 8.7, AC Electrical Characteristics).

While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the

status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished

and the device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL)

bit in the Status Register is cleared to 0. The Page Program instruction is not executed if the addressed page is

protected by the Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits.

Figure 7-22. Page Program Instruction (SPI Mode)

Figure 7-23. Page Program Instruction (QPI Mode)

AT25SF641 데이터시트(PDF) 32 Page - Dialog Semiconductor