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DA9072 데이터시트(PDF) 45 Page - Dialog Semiconductor |
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DA9072 데이터시트(HTML) 45 Page - Dialog Semiconductor |
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45 / 113 page ![]() DA9072 Ultra-Low Quiescent Current PMIC Datasheet Revision 3.0 14-Jun-2021 CFR0011-120-00 45 of 113 © 2021 Dialog Semiconductor DA9072 Host SCL MODE ROUT_N SYS_FLT PWR_FLT RIN_N (always-on) WD SDA Figure 27: Digital Pin Connections 4.8.1 Watchdog Input and Timer A programmable watchdog timer, WD, is available to detect a stall in the host. The WD function is enabled or disabled by bit WD_EN (register 0x0014 [1:0]). Each time the host initiates I2C or toggles the watchdog input, the timer resets. If no host activity is detected within the timeout period, the DA9072 toggles the SYS_FLT flag and sets the WD event bit, ISR_WD (register 0x0007 [4]), to 1. If the register reset on timeout option is enabled, bit WD_RST_REGS_EN (register 0x0014 [7]) the outputs are disabled for a period of typically 20 msec and then re-enabled to reset the host. The watchdog is automatically re-activated and the pre-programmed OTP values are loaded (except for RIN_N_RST_ROUT_EN and RIN_N_RST_REC at register 0x0010 [3:0]). The watchdog timeout period, tWATCHDOG in Figure 28, is programmable to 25 s or 50 s via WD_TMR_PER (register 0x0014 [5:4]). Optionally, the WD function can also toggle the ROUT_N pin, this is enabled by WD_ROUT_EN (register 0x0014 [6]). The WD_EN bits (register 0x0014 [1:0]) selects when the watchdog timer is enabled in different modes, see Table 36. Table 36: Watchdog Timer Enable Settings for Different Modes WD_EN Charge Mode Active Battery Mode Hi-Z Mode 0x00 Disable Disable Disable 0x01 Enable Disable Disable 0x02 Enable Enable Disable 0x03 Enable Enable Enable The WD_CLR_SEL bits (register 0x0014 [3:2]) select which activity the WD uses to clear the timer, see Table 37. Table 37: Watchdog Timer Clear Settings WD_CLR_SEL Description 0x00 Only I2C clears the timer 0x01 Only WD pin clears the timer 0x02 Both I2C and WD pin clear the timer 0x03 Reserved |
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