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DA9072 데이터시트(PDF) 35 Page - Dialog Semiconductor

부품명 DA9072
상세설명  Ultra-Low Quiescent Current PMIC
PDF  113 Pages
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DA9072
Ultra-Low Quiescent Current PMIC
Datasheet
Revision 3.0
14-Jun-2021
CFR0011-120-00
35 of 113
© 2021 Dialog Semiconductor
Figure 23: Typical Charging Example
Note 1
70 mAh Charge Cycle (VCHG_PRE = 3.0 V, ICHG_PRE = 7 mA, ICHG = 70 mA, VTER = 4.2 V)
4.4.2
Charge in Progress
Assuming a depleted battery, the battery is initially charged at ICHG_PRE until VBAT reaches the pre-
charge threshold, at which point the charge current is increased to ICHG. The charger continues to
charge at constant current (CC) until VBAT approaches the target voltage programmed by VBCHG
(register 0x0024:[6:0]). The battery is then charged at near constant voltage (CV) and the charge
current gradually falls. Charging ends when the charge current falls below ITER (ITER current is the
same as ICHG_PRE, see Section 4.7.1). If the VDD_PWR remains connected, recharging starts when
VBAT falls below the recharge threshold, VBAT_CHG - 120 mV (typical).
Charging modes are shown in Table 25.
Table 25: Charging Modes
VBAT Voltage
Charge Current
Charge Mode
Pre-Charge Timer
Main Timer
VBAT < VCHG_PRE
ICHG_PRE
Pre-charge
Running
Running
VCHG_PRE < VBAT < VBAT_CHG
ICHG
CC (fast charge)
Reset
Running
VBAT = VBAT_CHG
< ICHG
CV
Reset
Running
VBAT = VBAT_CHG
= ITER
Termination
Reset
Reset
From the charge ready state, the device enters charge in-progress state when all conditions below
are met.
● VDD_PWR > VBAT + VSLP (not in Sleep mode)
● VBAT < VRCHG
● RMEAS sequence completed, if enabled by RMEAS_EN (register 0x0020 [1])
● 50 ms TEMP_SNS delay, if periodic sampling is enabled by TS_DISCHG_MODE_SEL (register
0x0026 [5])
● MODE input is pulled low and CE_N register is set to 0
If these conditions are met, charging starts automatically at the appropriate level when VDD_PWR is
connected.



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