MDS 650-40A B

2

Revision 121004

ICS650-40A

Pin Assignment

Output Select Table (MHz)

Pin Descriptions

1

2

3

X2

4

VDD

5

6

7

8

VDDOA

GNDB

OE

GNDA

16

X1/ICLK

VDD

15

14

13

12

11

10

9

16-pin (173 mil) TSSOP

CLKA

CLKA

GNDA

S1

S0

GND

VDDOB

CLKB

S1

S0

CLKA

(MHz)

CLKA

(MHz)

CLKB

(MHz)

0

0

127

127

157

0

1

133

133

189

1

0

157

157

127

1

1

189

189

133

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

X1/ICLK

Input

Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.

2

VDD

Power

Connect to +3.3 V.

3

GNDA

Power

Connect to ground.

4

VDDOA

Power

Connect to +2.5 V or +3.3 V. For CLKA outputs only.

5

CLKA

Output

Clock A output with weak pull-down resistor.

6

CLKA

Output

Clock A output with weak pull-down resistor.

7

GNDA

Power

Connect to ground.

8

S1

Input

Select pin 1.

9

S0

Input

Select pin 0.

10

GNDB

Power

Connect to ground.

11

CLKB

Output

Clock B output with weak pull-down resistor.

12

VDDOB

Power

Connect to +2.5 V or 3.3 V. For clock output B only.

13

GND

Power

Connect to ground.

14

OE

Input

Output enable tri-states outputs and device is not shut down. This input

has internal pull-up resistor. OE = 1 enables outputs A and B and OE=0

disables outputs A and B. When disabled the pull-down resistor pulls the

outputs to GND.

15

VDD

Power

Connect to +3.3 V.

16

X2

Output

Crystal connection. Leave unconnected for clock input.