PCF8564A datasheet(55/86 Pages) NXP

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NXP Semiconductors

PCA2131

Nano-power highly accurate RTC with integrated quartz crystal for automotive applications

mbc621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Figure 29. Bit transfer

7.16.2.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH, is defined as the START condition S. A

LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition P (see Figure 30).

mbc622

SDA

SCL

STOP condition

SDA

SCL

START condition

Figure 30. Definition of START and STOP conditions

7.16.2.3 System configuration

A device generating a message is a transmitter; a device receiving a message is the

receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves.

The PCA2131 can act as a slave transmitter and a slave receiver.

mba605

MASTER

TRANSMITTER

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER

RECEIVER

SDA

SCL

Figure 31. System configuration

7.16.2.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge

cycle.

• A slave receiver which is addressed must generate an acknowledge after the reception

of each byte.

• Also a master receiver must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter.

PCA2131

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 26 July 2021

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