IMX7ULPCEC datasheet(24/118 Pages) NXP

24 / 118 page

chip modules as the external 32 kHz oscillator. The internal

oscillator is not precise relative to a crystal. While it will

provide a clock to the system, it generally will not be precise

enough for long-term time keeping. The internal oscillator is

anticipated to be useful for quicker start-up times and

tampering prevention, but should not be used as the exclusive

source for the 32 kHz clocks. An external 32 kHz clock

source must be used for production systems.

3 Application domain (implementing ARM Cortex-A7)

The application domain is built around an ARM Cortex-A7 processor optimized to run

nominally at 500 MHz, supported by a 32 KB L1 instruction and data cache, a large L2

cache, and an LPDDR2/LPDDR3 memory interface. The Cortex-A7 processor is a

high-performance low-power processor that implements the ARMv7-A architecture. It

uses the generic interrupt controller (GIC), generic 64-bit OS timer, FPU and the ARM

NEON SIMD engine. Additionally, all the optional debug features are included.

3.1 Memory system—application domain

3.1.1 Internal memory (application domain)

3.1.2 Multi Mode DDR Controller (MMDC)

The Multi Mode DDR Controller is a dedicated interface to LPDDR2/LPDDR3

SDRAM.

The i.MX 7ULP MMDC is compatible with the following JEDEC-compliant memory

types:

• LPDDR2 SDRAM compliant to JESD209-2F LPDDR2 JEDEC standard released

June, 2013

• LPDDR3 SDRAM compliant to JESD209-3C JEDEC standard released August,

2015

Application domain (implementing ARM Cortex-A7)

i.MX 7ULP Applications Processor—Consumer Products, Rev. 0, 06/2019

NXP Semiconductors

IMX7ULPCEC 데이터시트(PDF) 24 Page - NXP Semiconductors