| 전자부품 데이터시트 검색엔진 |
|
IMX7ULPCEC 데이터시트(PDF) 85 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
IMX7ULPCEC 데이터시트(HTML) 85 Page - NXP Semiconductors |
|
85 / 118 page ![]() Table 53. ADC electrical specifications (1V≤VREFH<VDD_ANA18MIN and VADINMAX≤VREFH)1 (continued) Symbol Description Min Typ2 Max Unit Notes EZS Zero-scale error 0.05 LSB 5 Iin_ext_leak External channel leakage current 30 500 nA EIL Input leakage error RAS * Iin mV 1. Values in this table are based on design simulations. 2. Typical values assume VDD_ANA_18 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are for reference only, and are not tested in production. 3. This resistance is external to the SoC. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. See Sample time vs. RAS. 5. 1 LSB = (VREFH - VREFL)/2N, N=12 6. ADC conversion clock at max frequency and using linear histogram. 7. Input data used for test was 1 kHz sine wave. The following figure shows a plot of the ADC sample time versus RAS. Figure 32. Sample time vs. RAS Specifications—real-time domain i.MX 7ULP Applications Processor—Consumer Products, Rev. 0, 06/2019 85 NXP Semiconductors |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |