DS31256_V01 datasheet(90/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

90 of 183

9.2.2 Packet Descriptors

A contiguous section of up to 65,536 quad dwords that make up the receive packet descriptors resides in

main memory. The receive packet descriptors are aligned on a quad dword basis and can be placed

anywhere in the 32-bit address space through the receive descriptor base address (Table 9-C). A data

buffer is associated with each descriptor. The data buffer can be up to 8188 Bytes long and must be a

contiguous section of main memory. The host can set two different data buffer sizes through the receive

large buffer size (RLBS) and the receive small buffer size (RSBS) registers (Section 9.2.1). If an

incoming packet requires more space than the data buffer allows, packet descriptors are link-listed

together by the DMA to provide a chain of data buffers. Figure 9-3 shows an example of how three

descriptors were linked together for an incoming packet on HDLC channel 2. Figure 9-2 shows a similar

example. Channel 9 only required a single data buffer and therefore only one packet descriptor was used.

Packet descriptors can be either free (available for use by the DMA) or used (currently contain data that

needs to be processed by the host). The free-queue descriptors point to the free-packet descriptors. The

done-queue descriptors point to the used-packet descriptors.

Table 9-C. Receive Descriptor Address Storage

NAME

ADDRESS

Receive Descriptor Base Address 0 (lower word)

RDBA0

0750h

Receive Descriptor Base Address 1 (upper word)

RDBA1

0754h

Figure 9-3. Receive Descriptor Example

Free Descriptor

Base + 00h

Channel 2 First Buffer Descriptor

Base + 10h

Base + 20h

Free Descriptor

Base + 30h

Free Descriptor

Base + 40h

Base + 50h

Free Descriptor

Base + 60h

Base + 70h

Free Descriptor

Base + 80h

Free Descriptor

Base + FFFD0h

Free Descriptor

Base + FFFF0h

Channel 9 Single Buffer Descriptor

Channel 2 Second Buffer Descriptor

Channel 2 Last Buffer Descriptor

Free-Queue Descriptor

Address

Done-Queue Descriptor Pointer

Maximum of 65,536

Descriptors

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