DS31256_V01 datasheet(13/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

13 of 183

3. SIGNAL DESCRIPTION

3.1 Overview/Signal List

This section describes the input and output signals on the DS31256. Signal names follow a convention

that is shown in the Signal Naming Convention table below. Table 3-A lists all the signals, their signal

type, description, and pin location.

Signal Naming Convention

FIRST LETTER

SIGNAL CATEGORY

SECTION

Receive Serial Port

3.2

Transmit Serial Port

3.2

Local Bus

3.3

JTAG Test Port

3.4

PCI Bus

3.5

Table 3-A. Signal Description

NAME

TYPE

FUNCTION

V19

JTCLK

JTAG IEEE 1149.1 Test Serial Clock

U18

JTDI

JTAG IEEE 1149.1 Test Serial Data Input

T17

JTDO

JTAG IEEE 1149.1 Test Serial Data Output

W20

JTMS

JTAG IEEE 1149.1 Test Mode Select

U19

JTRST

JTAG IEEE 1149.1 Test Reset

G20

LA0

I/O

Local Bus Address Bit 0, LSB

G19

LA1

I/O

Local Bus Address Bit 1

F20

LA2

I/O

Local Bus Address Bit 2

G18

LA3

I/O

Local Bus Address Bit 3

F19

LA4

I/O

Local Bus Address Bit 4

E20

LA5

I/O

Local Bus Address Bit 5

G17

LA6

I/O

Local Bus Address Bit 6

F18

LA7

I/O

Local Bus Address Bit 7

E19

LA8

I/O

Local Bus Address Bit 8

D20

LA9

I/O

Local Bus Address Bit 9

E18

LA10

I/O

Local Bus Address Bit 10

D19

LA11

I/O

Local Bus Address Bit 11

C20

LA12

I/O

Local Bus Address Bit 12

E17

LA13

I/O

Local Bus Address Bit 13

D18

LA14

I/O

Local Bus Address Bit 14

C19

LA15

I/O

Local Bus Address Bit 15

B20

LA16

I/O

Local Bus Address Bit 16

C18

LA17

I/O

Local Bus Address Bit 17

B19

LA18

I/O

Local Bus Address Bit 18

A20

LA19

I/O

Local Bus Address Bit 19, MSB

L20

LBGACK

Local Bus Grant Acknowledge

H20

LBHE

Local Bus Byte High Enable

J20

LCLK

Local Bus Clock

K19

LCS

Local Bus Chip Select

V20

LD0

I/O

Local Bus Data Bit 0, LSB

U20

LD1

I/O

Local Bus Data Bit 1

T18

LD2

I/O

Local Bus Data Bit 2

T19

LD3

I/O

Local Bus Data Bit 3

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