DS31256_V01 datasheet(103/183 Pages) MAXIM

103 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

103 of 183

- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -

dword 0; Bits 0 to 31/Current Data Buffer Address. The current 32-bit address of the data buffer that is being

used. This address is used by the DMA to track where data should be written to as it comes in from the receive

FIFO.

- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -

dword 1; Bits 0 to 15/Current Descriptor Pointer. This 16-bit value is the offset from the receive descriptor

base address of the current receive descriptor being used by the DMA to describe the specifics of the data stored in

the associated data buffer.

- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -

dword 1; Bits 16 to 31/Starting Descriptor Pointer. This 16-bit value is the offset from the receive descriptor

base address of the first receive descriptor in a link-list chain of descriptors. This pointer is written into the done

queue by the DMA after a specified number of data buffers (see the threshold value below) have been filled.

- HOST MUST CONFIGURE -

dword 2; Bit 0/Channel Enable (CHEN). This bit is controlled by the host to enable and disable an HDLC

channel.

0 = HDLC channel disabled

1 = HDLC channel enabled

- HOST MUST CONFIGURE -

dword 2; Bits 1, 2/Buffer Size Select. These bits are controlled by the host to select the manner in which the

receive DMA stores incoming packet data.

00 = use large size data buffers only

01 = use small size data buffers only

10 = fill a small buffer first, followed then by large buffers as needed

11 = illegal state and should not be selected

- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -

dword 2; Bits 3 to 6/DMA Reserved. These could be any value when read. They should be set to 0 when the host

writes to it.

- HOST MUST CONFIGURE -

dword 2; Bits 7 to 9/Threshold. These bits are controlled by the host to determine when the DMA should write

into the done queue that data is available for processing. They cannot be set to 000 when in transparent mode

(RTRANS = 1).

000 = DMA should write to the done queue only after packet reception is complete

001 = DMA should write to the done queue after 1 data buffer has been filled

010 = DMA should write to the done queue after 2 data buffers have been filled

011 = DMA should write to the done queue after 3 data buffers have been filled

100 = DMA should write to the done queue after 4 data buffers have been filled

101 = DMA should write to the done queue after 5 data buffers have been filled

110 = DMA should write to the done queue after 6 data buffers have been filled

111 = DMA should write to the done queue after 7 data buffers have been filled

- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -

dword 2; Bits 10 to 14/DMA Reserved. These could be any value when read. They should be set to 0 when the

host writes to it.

- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -

dword 2; Bit 15/First Buffer Fill (FBF). This bit is set to 1 by the receive DMA when it is in the process of

filling the first buffer of a packet. The DMA uses this bit to determine when to switch to large buffers when the

buffer size-select field is set to 10.

DS31256 데이터시트(PDF) 103 Page - Maxim Integrated Products

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