DS31256 datasheet(65/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

65 of 183

BERTBC0

BERT 32-Bit Bit Counter (lower word)

0510h

BERTBC1

BERT 32-Bit Bit Counter (upper word)

0514h

BERTBC0: BERT Bit Counter 0 (lower word)

Bit #

Name

BERT 32-Bit Bit Counter (lower byte)

Default

Bit #

Name

BERT 32-Bit Bit Counter

Default

BERTBC1: BERT Bit Counter 0 (upper word)

Bit #

Name

BERT 32-Bit Bit Counter

Default

Bit #

Name

BERT 32-Bit Bit Counter (upper byte)

Default

Note: Bits that are underlined are read-only; all other bits are read-write

Bits 0 to 31/BERT 32-Bit Bit Counter (BERTBC0 and BERTBC1). This 32-bit counter increments for each

data bit (i.e., clock) received. This counter is not disabled when the receive BERT loses synchronization. This

counter is loaded with the current bit count value when the LC control bit in the BERTC0 register is toggled from

low (0) to high (1). When full, this counter saturates and sets the BBCO status bit.

BERTEC0

BERT 24-Bit Error Counter (lower) and Status Information

0518h

Bit #

Name

n/a

RA1

RA0

RLOS

BED

BBCO

BECO

SYNC

Default

Bit #

Name

BERT 24-Bit Error Counter (lower byte)

Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 0/Real-Time Synchronization Status (SYNC). Real-time status of the synchronizer (this bit is not latched). Is

set when the incoming pattern matches for 32 consecutive bit positions. Is cleared when six or more bits out of 64

are received in error.

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