DS31256 datasheet(78/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

78 of 183

block pointer RAM, the host should write this bit to 0. This causes the device to take the data that is currently

present in the RFBP register and write it to the channel location indicated by the BLKID bits. When the device

completes the write, the IAB is set to 0.

Note: The RFSBP is write-only memory. Once this register has been written to and the operation has started, the

DS31256 internal state machine changes the value in this memory.

Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set

to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is

ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the

write operation completes.

RFBP

Receive FIFO Block Pointer

0914h

Bit #

Name

RBP7

RBP6

RBP5

RBP4

RBP3

RBP2

RBP1

RBP0

Default

Bit #

Name

n/a

RBP9

RBP8

Default

Note: Bits that are underlined are read only, all other bits are read-write.

Bits 0 to 9/Block Pointer (RBP0 to RBP9). These bits indicate which of the 10242 blocks is the next block in the

link-list chain. A block is not allowed to point to itself.

0000000000 (000h) = block 0 is the next linked block

0111111111 (1FFh) = block 511 is the next linked block

1111111111 (3FFh) = block 1023 is the next linked block

RFHWMIS

Receive FIFO High-Watermark Indirect Select

0920h

Bit #

Name

HCID7

HCID6

HCID5

HCID4

HCID3

HCID2

HCID1

HCID0

Default

Bit #

Name

IAB

IARW

n/a

Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7)

00000000 (00h) = HDLC channel number 1

11111111 (FFh) = HDLC channel number 256

Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal receive high-

watermark RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining the data

from the channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data

is ready to be read from the RFHWM register, the IAB bit is set to 0. When the host wishes to write data to the

internal receive high-watermark RAM, this bit should be written to 0 by the host. This causes the device to take

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