DS31256 datasheet(67/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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7. HDLC

7.1 General Description

The DS31256 contains two different types of HDLC controllers. Each port has a slow HDLC engine

(type #1) associated with it that can operate in either a channelized mode up to 8.192Mbps or an

unchannelized mode at rates up to 10Mbps. Ports 0 and 1 also have an additional fast HDLC engine

(type #2) that can operate in only an unchannelized fashion up to 52Mbps. Through the Layer 1 registers

(Section 6.2), the host determines which type of HDLC controller is used on a port and if the HDLC

controller is to be operated in either a channelized or unchannelized mode. If the HDLC controller is to

be operated in the channelized mode, then the Layer 1 registers (Section 6.3) also determine which

HDLC channels are associated with which DS0 channels. If the fast HDLC engine is enabled on port 0,

HDLC channel 1 is assigned to it and, likewise, HDLC channel 2 is assigned to the fast HDLC engine on

port 1 if it is enabled.

The HDLC controllers can handle all required normal real-time tasks. Table 7-B lists all the functions

supported by the receive HDLC and Table 7-C lists all the functions supported by the transmit HDLC.

Each of the 256 HDLC channels within the DS31256 are configured by the host through the receive

HDLC channel definition (RHCD) and transmit channel definition (THCD) registers. There is a separate

RHCD and THCD register for each HDLC channel. The host can access the RHCD and THCD registers

indirectly through the RHCDIS indirect select and THCDIS indirect select registers. See Section 7.2 for

details.

On the receive side, one of the outcomes shown in Table 7-A occurs when the HDLC block is processing

a packet. For each packet, one of these outcomes is reported in the receive done-queue descriptor

(Section 9.2.4). On the transmit side, when the HDLC block is processing a packet, an error in the PCI

block (parity or target abort) or transmit FIFO underflow causes the HDLC block to send an abort

sequence (eight 1s in a row) followed continuously by the selected interfill (either 7Eh or FFh) until the

HDLC channel is reset by the transmit DMA block (Section 9.3.1). This same sequence of events will

occur even if the transmit HDLC channel is being operated in the transparent mode. In the transparent

mode, when the FIFO empties the device sends either 7Eh or FFh.

If any of the 256 receive HDLC channels detects an abort sequence, an FCS checksum error, or if the

packet length was incorrect, then the appropriate status bit in SDMA is set. If enabled, the setting of any

of these statuses can cause a hardware interrupt to occur. See Section 5.3.2 for details about the operation

of these status bits.

Table 7-A. Receive HDLC Packet Processing Outcomes

OUTCOME

CRITERIA

EOF/Normal Packet

Integral number of packets > min and < max is received and CRC is okay

EOF/Bad FCS

Integral number of packets > min and < max is received and CRC is bad

Abort Detected

Seven or more 1s in a row detected

EOF/Too Few Bytes

Fewer than 4 or 6 Bytes received

Too Many Bytes

Greater than the packet maximum is received (if detection enabled)

EOF/Bad # of Bits

Not an integral number of bytes received

FIFO Overflow

Tried to write a byte into an already full FIFO

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