 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
DS31256 데이터시트(PDF) 171 Page - Maxim Integrated Products |
|
|
|||||||||||||||||||||||||||||
DS31256 데이터시트(HTML) 171 Page - Maxim Integrated Products |
|
|
171 / 183 page  DS31256 256-Channel, High-Throughput HDLC Controller 171 of 183 AC CHARACTERISTICS: LOCAL BUS IN CONFIGURATION MODE (LMS = 1) (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Setup Time for LA[15:0] Valid to LCS Active t1 0 ns Setup Time for LCS Active to Either LRD, LWR, or LDS Active t2 0 ns Delay Time from Either LRD or LDS Active to LD[15:0] Valid t3 (Note 12) 75 ns Hold Time from Either LRD, LWR, or LDS Inactive to LCS Inactive t4 0 ns Hold Time from Either LRD or LDS Inactive to LD[15:0] Tri-State t5 5 20 ns Wait Time from Either LWR or LDS Active to Latch LD[15:0] t6 (Note 13) 75 ns LD[15:0] Setup Time to Either LWR or LDS Inactive t7 10 ns LD[15:0] Hold Time from Either LWR or LDS Inactive t8 2 ns LA[15:0] Hold from Either LWR, LRD, or LDS Inactive t9 5 ns LRD, LWD, or LDS Inactive Time t10 (Note 14) 65 ns Note 12: Given value for 33MHz PCLK. Calculated as 1.5 x (PCLK Period) + 30ns Note 13: Given value for 33MHz PCLK. Calculated as 2 x (PCLK Period) + 15ns Note 14: Given value for 33MHz PCLK. Calculated as 2 x (PCLK Period) + 5ns |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
