P87LPC779FDH datasheet(37/74 Pages) PHILIPS

37 / 74 page

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

Product data

Rev. 02 — 03 May 2004

37 of 74

9397 750 13213

In addition to this, the CPU clock may be divided down from the oscillator rate by a

programmable divider, under program control. This function is controlled by the DIVM

by either the unmodiﬁed oscillator rate, or that rate divided by two, as determined by

the previously described CLKR function.

When the DIVM register is set to some value N (between 1 and 255), the CPU clock

is divided by 2

× (N + 1). Clock division values from 4 through 512 are thus possible.

This feature makes it possible to temporarily run the CPU at a lower rate, reducing

power consumption, in a manner similar to Idle mode. By dividing the clock, the CPU

can retain the ability to respond to events other than those that can cause interrupts

(i.e., events that allow exiting the Idle mode) by executing its normal program at a

lower rate. This can allow bypassing the oscillator startup time in cases where

Power-down mode would otherwise be used. The value of DIVM may be changed by

the program at any time without interrupting code execution.

8.11 Power monitoring functions

The P87LPC779 incorporates power monitoring functions designed to prevent

incorrect operation during initial power up and power loss or reduction during

operation. This is accomplished with two hardware functions: Power-On Detect and

Brownout Detect.

8.11.1

Brownout detection

The Brownout Detect function helps prevent the processor from failing in an

unpredictable manner if the power supply voltage drops below a certain level. The

default operation is for a brownout detection to cause a processor reset, however it

may alternatively be conﬁgured to generate an interrupt by setting the BOI bit in the

AUXR1 register (AUXR1.5).

The P87LPC779 allows selection of two Brownout levels: 2.5 V or 3.8 V. When VDD

drops below the selected voltage, the brownout detector triggers and remains active

until VDD is returns to a level above the Brownout Detect voltage. When Brownout

Detect causes a processor reset, that reset remains active as long as VDD remains

below the Brownout Detect voltage. When Brownout Detect generates an interrupt,

that interrupt occurs once as VDD crosses from above to below the Brownout Detect

voltage. For the interrupt to be processed, the interrupt system and the BOI interrupt

must both be enabled (via the EA and EBO bits in IEN0).

When Brownout Detect is activated, the BOF ﬂag in the PCON register is set so that

the cause of processor reset may be determined by software. This ﬂag will remain set

until cleared by software.

For correct activation of Brownout Detect, the VDD fall time must be no faster than

50 mV/

µs. When V

DD is restored, is should not rise faster than 2 mV/µs in order to

insure a proper reset.

The brownout voltage (2.5 V or 3.8 V) is selected via the BOV bit in the EPROM

conﬁguration register UCFG1. When unprogrammed (BOV = 1), the brownout detect

voltage is 2.5 V. When programmed (BOV = 0), the brownout detect voltage is 3.8 V.

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