P87LPC779FDH datasheet(41/74 Pages) PHILIPS

41 / 74 page

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

Product data

Rev. 02 — 03 May 2004

41 of 74

9397 750 13213

8.14 Timer/counters

The P87LPC779 has two general purpose counter/timers which are upward

compatible with the standard 80C51 Timer0 and Timer1. Both can be conﬁgured to

operate either as timers or event counters (see Tables 31 and 32). An option to

automatically toggle the T0 and/or T1 pins upon timer overﬂow has been added.

In the ‘Timer’ function, the register is incremented every machine cycle. Thus, one

can think of it as counting machine cycles. Since a machine cycle consists of 6 CPU

clock periods, the count rate is 1

⁄

6 of the CPU clock frequency. Refer to Section 8.1

“Enhanced CPU” on page 12 for a description of the CPU clock.

In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition

at its corresponding external input pin, T0 or T1. In this function, the external input is

sampled once during every machine cycle. When the samples of the pin state show a

high in one cycle and a low in the next cycle, the count is incremented. The new count

value appears in the register during the cycle following the one in which the transition

was detected. Since it takes 2 machine cycles (12 CPU clocks) to recognize a 1-to-0

transition, the maximum count rate is 1

⁄6 of the CPU clock frequency. There are no

restrictions on the duty cycle of the external input signal, but to ensure that a given

level is sampled at least once before it changes, it should be held for at least one full

machine cycle.

The ‘Timer’ or ‘Counter’ function is selected by control bits C/T in the Special

Function Register TMOD. In addition to the ‘Timer’ or ‘Counter’ selection, Timer0 and

Timer1 have four operating modes, which are selected by bit-pairs (M1, M0) in

TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different.

The four operating modes are described in the following text.

Fig 18. Block diagram showing reset sources.

002aaa636

RPD (UCFG1.6)

RST / VPP pin

WDTE (UCFG1.7)

WDT

MODULE

SOFTWARE RESET

SRST

(AUXR1.3)

POWER MONITOR

RESET

chip reset

RESET

TIMING

CPU

clock

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