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ADP5360ACBZ-2-R7 데이터시트(PDF) 57 Page - Analog Devices

부품명 ADP5360ACBZ-2-R7
상세설명  Advanced Battery Management PMIC with Ultra Low Power Buck and Buck Boost
PDF  60 Pages
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ADP5360ACBZ-2-R7 데이터시트(HTML) 57 Page - Analog Devices

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Data Sheet
ADP5360
Rev. 0 | Page 57 of 60
PCB LAYOUT GUIDELINES
Poor layout can affect ADP5360 performance, causing EMI and
electromagnetic compatibility (EMC) problems, ground bounce,
and voltage losses, as well as affect regulation and stability. A
good layout is implemented using the following guidelines:
•
Place the decoupling capacitor, inductor, input capacitor,
and output capacitor as close as possible to the ADP5360.
•
Use a ground plane with several vias connecting to the
component side ground to further reduce noise
interference on sensitive circuit nodes.
•
Use a dedicated trace to connect the BSNS pin to the
battery pack output node for accurate sensing of the
battery voltage.
•
Use 0603 size or 0402 size resistors and capacitors to
achieve the smallest possible footprint solution on boards
where space is limited.
STP
SDA
INT
ENSD
EN2
PGND1
PGOOD1
ENCHG
SCL
THR
ILIM
PGOOD2
VDD
ISOB
MR
A
B
C
D
E
1
2
3
4
FB1
SW1
SW2B
5
PGND2
VIN2
SW2A
VIN1
AGND
RESET
VSYS
F
6
BSNS
AGND
VID1
EN1
ICS
VBUS
L1
4.7µH
0806
C1
2.2µF
25V/X5R
0402
C3
10µF
6.3V/X5R
0402
C4
10µF
6.3V/X5R
0402
C6
10µF
6.3V/X5R
0402
L2
4.7µH
0806
C8
10µF
6.3V/X5R
0402
PGND
TOP LAYER
BOTTOM LAYER
TO MCU
ADP5360
5mm
7mm
TO
BATTERY
C5
10µF
6.3V/X5R
0402
C2
1µF
6.3V/X5R
0402
C7
10µF
6.3V/X5R
0402
VOUT1
VSYS
VOUT2
PGND
VBUS
ISOB
VOUT2
Figure 62. Recommend Layout



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