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AS3977

Data Sheet - A p p l i c a t i o n I n f o r m a t i o n

Software Power Down Method.

long as the bit is set to high.

9.3.2 Active Edge of CLK

When the Power Down Mode is left, the level of CLK at the rising edge of ENABLE determines the active edge of CLK (CLK polarity). Once the

CLK polarity is set, it stays unchanged until the next Power Down Mode is re-entered.

9.3.3 Active State

The Active state is entered at the rising edge of ENABLE, which as well resets the Power Down timer. Possible previous states are Power Down

Mode, Transmit state. DATAIO is set to SDI data input and the Interface expects a command control byte to configure the state-machine. The

SDI state can be left by programming another state or by setting ENABLE low for more than 2

9.3.4 Transmit State

The state is entered upon command. The transmit command byte defines in combination with the configuration registers the transmit

configuration. The power amplifier (PA) will be activated on the subsequent sampling edge of CLK after receiving the command byte only if the

lock transmit bit has been reset (0) by a previous SDI command. Here (only here) the baud rate and data generator counters are reset, i.e. if

Transmit was interrupted by a SDI communication and is re-entered again (with active PA), the baud rate generator is kept synchronized with the

previous transmitted string. DATAIO is set to TX data input. If during transmit a low power reset (LPR) occurs, the lock transmit bit is set high and

hence the power amplifier is switched off.

The state can be left at the falling edge of ENABLE, or increasing the Supply Voltage above the threshold and setting the register bit (LT) to zero.

The control of the power amplifier is determined by the command byte (bit A4 and A5).

Step

Software Power Down Method

1

Set power Down Bit =1 and put ENABLE to LOW level

2

Power on reset complete with next xtal cycle

State

ENABLE

LT

Description

Power Down Mode

↑

1

LT is set to High

All other states

↑

LT is unchanged except the Supply

voltage drops down below the

threshold level

State

ENABLE

CLK

Description

Power Down Mode

↑

0

DATAIO is sampled at the falling edge of CLK

Power Down Mode

↑

1

DATAIO is sampled at the rising edge of CLK

All other states

↑

X

CLK behavior is unchanged

Table 20. PA Control Modes

State

LT

A4

A5

ENABLE

Description

All States

1

X

X

X

PAON low

Transmit

0

X

X

1

PAON high on the subsequent sampling edge of CLK after

receiving the command byte

Transmit

0

0

0

↓

PAON low at the falling edge of ENABLE

Transmit

0

0

1

↓

PAON low at the falling edge of ENABLE but synchronized with

baud rate, DATAIO is latched

Transmit

0

1

X

↓

PAON stays high, DATAIO is latched