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EDB8164B4PT-1DITF-R 데이터시트(PDF) 40 Page - Micron Technology

부품명 EDB8164B4PT-1DITF-R
상세설명  216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Features
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4. If ZQ is connected to VSS through RZQ, either the ZQ calibration function (see MODE
REGISTER WRITE command) or default calibration (through the ZQRESET command) is
supported. If ZQ is connected to VDD2, the device operates with default calibration, and
ZQ calibration commands are ignored. In both cases, the ZQ connection must not
change after power is supplied to the device.
5. LPDDR2 devices that do not support calibration shall ignore the ZQ Calibration com-
mand.
6. Optionally, the MRW ZQ Initialization Calibration command will update MR0 to indicate
RZQ pin connection.
Table 36: MR[11:15] Reserved (MA[7:0] = 0Bh–0Fh)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Reserved
Table 37: MR16 PASR Bank Mask (MA[7:0] = 010h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Bank mask (4-bank or 8-bank)
Table 38: MR16 Op-Code Bit Definitions
Feature
Type
OP
Definition
Bank[7:0] mask
Write-only
OP[7:0]
0b: refresh enable to the bank = unmasked (default)
1b: refresh blocked = masked
Note:
1. For 4-bank devices, only OP[3:0] are used.
Table 39: MR16 Bank and OP corresponding table
Feature
Type
OP
4-Bank Mask
8-Bank Mask
Bank #
Bank
Address
Bank #
Bank
Address
Bank[7:0] mask
Write-only
0
Bank 0
000b
Bank 0
000b
1
Bank 1
001b
Bank 1
001b
2
Bank 2
010b
Bank 2
010b
3
Bank 3
011b
Bank 3
011b
4
–
–
Bank 4
100b
5
–
–
Bank 5
101b
6
–
–
Bank 6
110b
7
–
–
Bank 7
111b
Note:
1. Each bank can be masked independently by setting each OP value.
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
Mode Register Definition
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
40
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.



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